library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity decoder4x16 is
port(
  Op   : in std_logic_vector(3 downto 0);
  en   : out std_logic_vector(15 downto 0)
);
end decoder4x16;

architecture rtl of decoder4x16 is
begin
	en(0) 	<= (not Op(3)) and (not Op(2)) and (not Op(1)) and (not Op(0));
	en(1) 	<= (not Op(3)) and (not Op(2)) and (not Op(1)) and Op(0);
	en(2) 	<= (not Op(3)) and (not Op(2)) and Op(1) and (not Op(0));
	en(3) 	<= (not Op(3)) and (not Op(2)) and Op(1) and Op(0);
	en(4) 	<= (not Op(3)) and Op(2) and (not Op(1)) and (not Op(0));
	en(5) 	<= (not Op(3)) and Op(2) and (not Op(1)) and Op(0);
	en(6) 	<= (not Op(3)) and Op(2) and Op(1) and (not Op(0));
	en(7) 	<= (not Op(3)) and Op(2) and Op(1) and Op(0);
	en(8) 	<= (Op(3)) and (not Op(2)) and (not Op(1)) and (not Op(0));
	en(9) 	<= (Op(3)) and (not Op(2)) and (not Op(1)) and Op(0);
	en(10) 	<= (Op(3)) and (not Op(2)) and Op(1) and (not Op(0));
	en(11) 	<= (Op(3)) and (not Op(2)) and Op(1) and Op(0);
	en(12) 	<= (Op(3)) and Op(2) and (not Op(1)) and (not Op(0));
	en(13) 	<= (Op(3)) and Op(2) and (not Op(1)) and Op(0);
	en(14) 	<= (Op(3)) and Op(2) and Op(1) and (not Op(0));
	en(15) 	<= (Op(3)) and Op(2) and Op(1) and Op(0);
end architecture rtl;